module driver(
/*AUTOARG*/
   // Outputs
   tx_rdy, command_valid, command, error_en, error_data, data_req,
   data_valid, data_from_ip, addr_valid, address, hdr_valid, cycle,
   tag, length, message_valid, message_code, message_specific,
   // Inputs
   clk, rst
   );



parameter  UART_ADDR = 16'h03f8 ;
parameter  LED_ADDR  = 16'h0080 ;


////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

input           clk ;
input           rst ;

output               tx_rdy   ;

output wire 		command_valid		;
output wire	[7:0]	command			;
output wire		error_en		;
output wire	[15:0]	error_data		;
output wire		data_req		;
output reg 		data_valid		;
output reg 	[7:0]	data_from_ip		;


output reg 	[2:0]	addr_valid		;
output reg 	[63:0]	address			;
output wire		hdr_valid		;
output wire	[7:0]	cycle			;
output wire	[3:0]	tag			;
output wire	[11:0]	length			;
output wire		message_valid		;
output wire	[7:0]	message_code		;
output wire	[31:0]	message_specific	;


reg        [1:0]             addr_flag               ;

reg                     tx_rdy   ;

//////////////////////////////////////////////////////////////////////////////////

reg [ 7 : 0]   test_cnt ;
always@ ( posedge rst  or posedge clk)
begin
  if ( rst ) begin
     test_cnt  <=  'd0 ;
  end
  else begin 
     test_cnt  <=  test_cnt + 1'b1;
  end
end


always@ ( posedge rst  or posedge clk)
begin
  if ( rst ) begin
     addr_valid  <=  'd0 ;
  end
  else begin 
     addr_valid  <=  (test_cnt[4:0] == 5'd4)  ;
  end
end
//addr_flag
always@ ( posedge rst  or posedge clk)
begin
  if ( rst ) begin
     addr_flag  <=  'd0 ;
  end
  else begin 
     addr_flag  <=  addr_valid ?  addr_flag + 1'd1  :  addr_flag  ;
  end
end

always@ ( posedge rst  or posedge clk)
begin
  if ( rst ) begin
     address  <=  UART_ADDR  ;
  end
  else if ((test_cnt[4:0] == 4'd4) )  begin 
     address  <=   (addr_flag==0) ?   UART_ADDR :
                   (addr_flag==1) ?   LED_ADDR  :  $random           ;
  end
end

//data_valid
//data_from_ip
always@ ( posedge rst  or posedge clk)
begin
  if ( rst ) begin
     data_valid  <=  'd0 ;
  end
  else begin 
     data_valid  <=  (test_cnt[4:0] >= 5'd5)  &&   (test_cnt[4:0] <= 5'd6)    ;
  end
end
always@ ( posedge rst  or posedge clk)
begin
  if ( rst ) begin
     data_from_ip  <=  'd0 ;
  end
  else begin 
     data_from_ip  <= data_valid  ?   data_from_ip + 'd1   :   data_from_ip   ;
  end
end



//tx_rdy
always@ ( posedge rst  or posedge clk)
begin
  if ( rst ) begin
     tx_rdy  <=  'd0 ;
  end
  else begin 
     tx_rdy  <= $random  ;
  end
end



endmodule

